CSC305: Computer Architecture

Introduction

• What’s New in the Eleventh Edition
• Support of ACM/IEEE Computer Science and Computer Engineering Curricula
• Objectives
• Example Systems
• Plan of the Text

Basic Concepts and Computer Evolution

• Organization and Architecture
• Structure and Function
• The IAS Computer
• Gates, Memory Cells, Chips, and Multichip Modules
• The Evolution of the Intel x86 Architecture
• Embedded Systems
• ARM Architecture

Performance Concepts

• Designing for Performance
• Multicore, Mics, and GPGPUs
• Two Laws that Provide Insight: Amdahl's Law and Little’s Law
• Basic Measures of Computer Performance
• Calculating the Mean
• Benchmarks and Spec

A Top-Level View of Computer Function and Interconnection

• Computer Components
• Computer Function
• Interconnection Structures
• Bus Interconnection
• Point-to-Point Interconnect
• PCI Express

The Memory Hierarchy: Locality and Performance

• Principle of Locality
• Characteristics of Memory Systems
• The Memory Hierarchy
• Performance Modeling of a Multilevel Memory Hierarchy

Cache Memory

• Cache Memory Principles
• Elements of Cache Design
• Intel x86 Cache Organization
• The IBM z13 Cache Organization
• Cache Performance Models

Internal Memory

• Semiconductor Main Memory
• Error Correction
• DDR DRAM
• eDRAM
• Flash Memory
• Newer Nonvolatile Solid-State Memory Technologies

External Memory 

• Magnetic Disk
• RAID
• Solid State Drives
• Optical Memory
• Magnetic Tape

Input/Output

• External Devices
• I/O Modules
• Programmed I/O
• Interrupt-Driven I/O
• Direct Memory Access
• Direct Cache Access
• I/O Channels and Processors
• External Interconnection Standards
• IBM z13 I/O Structure

Operating System Support

• Operating System Overview
• Scheduling
• Memory Management
• Intel x86 Memory Management
• ARM Memory Management

Number Systems

• The Decimal System
• Positional Number Systems
• The Binary System
• Converting Between Binary and Decimal
• Hexadecimal Notation

Computer Arithmetic

• The Arithmetic and Logic Unit
• Integer Representation
• Integer Arithmetic
• Floating-Point Representation
• Floating-Point Arithmetic

Digital Logic

• Boolean Algebra
• Gates
• Combinational Circuits
• Sequential Circuits
• Programmable Logic Devices

Instruction Sets: Characteristics and Functions

• Machine Instruction Characteristics
• Types of Operands
• Intel x86 and ARM Data Types
• Types of Operations
• Intel x86 and ARM Operation Types
• Appendix 13A Little-, Big-, and Bi-Endian

Instruction Sets: Addressing Modes and Formats

• Addressing Modes
• x86 and ARM Addressing Modes
• Instruction Formats
• x86 and ARM Instruction Formats

Assembly Language and Related Topics

• Assembly Language Concepts
• Motivation For Assembly Language Programming
• Assembly Language Elements
• EXAMPLES
• Types of assemblers
• Assemblers
• Loading and Linking

Processor Structure and Function

• Processor Organization
• Register Organization
• Instruction Cycle
• Instruction Pipelining
• Processor Organization for Pipelining
• The x86 Processor Family
• The ARM Processor

Reduced Instruction Set Computers

• Instruction Execution Characteristics
• The Use of a Large Register File
• Compiler-Based Register Optimization
• Reduced Instruction Set Architecture
• RISC Pipelining
• MIPS R4000
• SPARC
• Processor Organization For Pipelining
• CISC, RISC, And Contemporary Systems

Instruction-Level Parallelism and Superscalar Processors

• Overview
• Design Issues
• Intel Core Microarchitecture
• ARM Cortex-A8
• ARM Cortex-M3

Control Unit Operation and Microprogrammed Control

• Micro-Operations
• Control of the Processor
• Hardwired Implementation
• Microprogrammed Control

Parallel Processing

• Multiple Processor Organizations
• Symmetric Multiprocessors
• Cache Coherence and the MESI Protocol
• Multithreading and Chip Multiprocessors
• Clusters
• Nonuniform Memory Access

Multicore Computers

• Hardware Performance Issues
• Software Performance Issues
• Multicore Organization
• Heterogeneous Multicore Organization
• INTEL Core i7-5960X
• ARM Cortex-A15 MPCore
• IBM z13 Mainframe

Appendix A: System Buses

• A.1 Bus Structure
• A.2 Multiple-Bus Hierarchies
• A.3 Elements of Bus Design

Appendix B: Victim Cache Strategies

• B.1 Victim Cache
• B.2 Selective Victim Cache

Appendix C: Interleaved Memory

Appendix D: The International Reference Alphabet

Appendix E: Stacks

• E.1 Stacks
• E.2 Stack Implementation
• E.3 Expression Evaluation

Appendix F: Recursive Procedures

• F.1 Recursion
• F.2 Activation Tree Representation
• F.3 Stack Implementation
• F.4 Recursion and Iteration

Appendix G: Additional Instruction Pipeline Topics

• G.1 Pipeline Reservation Tables
• G.2 Reorder Buffers
• G.3 Tomasulo’s Algorithm
• G.4 Scoreboarding