UOP-CSS421: Computer Organization and Architecture

• Organization and Architecture
• Structure and Function
• The IAS Computer
• Gates, Memory Cells, Chips, and Multichip Modules
• The Evolution of the Intel x86 Architecture
• Embedded Systems
• ARM Architecture
• Designing for Performance
• Multicore, Mics, and GPGPUs
• Two Laws that Provide Insight: Amdahl's Law and Little’s Law
• Basic Measures of Computer Performance
• Calculating the Mean
• Benchmarks and Spec
• Computer Components
• Computer Function
• Interconnection Structures
• Bus Interconnection
• Point-to-Point Interconnect
• PCI Express
• Principle of Locality
• Characteristics of Memory Systems
• The Memory Hierarchy
• Performance Modeling of a Multilevel Memory Hierarchy
• Appendix A: System Buses

7 LiveLab in this lesson — see the labs panel →

• Cache Memory Principles
• Elements of Cache Design
• Intel x86 Cache Organization
• The IBM z13 Cache Organization
• Cache Performance Models
• Semiconductor Main Memory
• Error Correction
• DDR DRAM
• eDRAM
• Flash Memory
• Newer Nonvolatile Solid-State Memory Technologies
• Magnetic Disk
• RAID
• Solid State Drives
• Optical Memory
• Magnetic Tape
• External Devices
• I/O Modules
• Programmed I/O
• Interrupt-Driven I/O
• Direct Memory Access
• Direct Cache Access
• I/O Channels and Processors
• External Interconnection Standards
• IBM z13 I/O Structure
• Operating System Overview
• Scheduling
• Memory Management
• Intel x86 Memory Management
• ARM Memory Management

8 LiveLab in this lesson — see the labs panel →

• The Decimal System
• Positional Number Systems
• The Binary System
• Converting Between Binary and Decimal
• Hexadecimal Notation
• The Arithmetic and Logic Unit
• Integer Representation
• Integer Arithmetic
• Floating-Point Representation
• Floating-Point Arithmetic
• Boolean Algebra
• Gates
• Combinational Circuits
• Sequential Circuits
• Programmable Logic Devices

3 LiveLab in this lesson — see the labs panel →

• Machine Instruction Characteristics
• Types of Operands
• Intel x86 and ARM Data Types
• Types of Operations
• Intel x86 and ARM Operation Types
• Appendix 13A Little-, Big-, and Bi-Endian
• Addressing Modes
• x86 and ARM Addressing Modes
• Instruction Formats
• x86 and ARM Instruction Formats
• Assembly Language Concepts
• Motivation For Assembly Language Programming
• Assembly Language Elements
• EXAMPLES
• Types of assemblers
• Assemblers
• Loading and Linking
• Processor Organization
• Register Organization
• Instruction Cycle
• Instruction Pipelining
• Processor Organization for Pipelining
• The x86 Processor Family
• The ARM Processor
• Instruction Execution Characteristics
• The Use of a Large Register File
• Compiler-Based Register Optimization
• Reduced Instruction Set Architecture
• RISC Pipelining
• MIPS R4000
• SPARC
• Processor Organization For Pipelining
• CISC, RISC, And Contemporary Systems

5 LiveLab in this lesson — see the labs panel →

• Overview
• Design Issues
• Intel Core Microarchitecture
• ARM Cortex-A8
• ARM Cortex-M3
• Micro-Operations
• Control of the Processor
• Hardwired Implementation
• Microprogrammed Control
• Multiple Processor Organizations
• Symmetric Multiprocessors
• Cache Coherence and the MESI Protocol
• Multithreading and Chip Multiprocessors
• Clusters
• Nonuniform Memory Access
• Hardware Performance Issues
• Software Performance Issues
• Multicore Organization
• Heterogeneous Multicore Organization
• INTEL Core i7-5960X
• ARM Cortex-A15 MPCore
• IBM z13 Mainframe
• Appendix G: Additional Instruction Pipeline Topics

7 LiveLab in this lesson — see the labs panel →